View M52342FP_8223826.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev.2.00 jun 14, 2006 page 1 of 18 M52342FP pll-split vif/sif ic rej03f0165-0200 rev.2.00 jun 14, 2006 description the M52342FP is if signal-processing ic for vcrs and tvs. it enables the pll detection system despite size as small as that of conventional quasi-synchronous vif/sif detector, if/rf agc, sif limiter, fm detector, qif agc and eq amp. features ? video detection output is 2 v p-p . it has built-in eq amp. ? the package is a 24-pin flat p ackage, suitable for space saving. ? the video detector uses pll for full synchronous detection circuit. it produces excellent characteristics of dg, dp, 920 khz beat, and cross color. ? dynamic agc realizes high-speed response with only single filter. ? video if and sound if signal pr ocessing are separated from each other. vco output is used to obtain intercarrier. this pll-split method and built-in qif agc provide good sound sensitivity and reduces buzz. ? as aft output voltage uses the apc output voltage, vco coil is not used. ? audio fm demodulation uses pll system, so it has wide frequency range with no external parts and no adjustment. application tv sets, vcr tuners recommended operating condition ? in case of v cc and vreg. out short ? supply voltage range: 4.75 to 5.25 v ? recommended supply voltage: 5.0 v ? incase of vreg. out open ? supply voltage range: 8.5 to 12.5 v
M52342FP rev.2.00 jun 14, 2006 page 2 of 18 block diagram vif amp rf agc delay gnd 1 2 3 4 5 6 7 8 gnd if agc filter 9 10 qif det in audio out 11 12 nfb gnd vif in vif in rf agc out apc filter 24 23 22 21 20 19 18 17 eq f/b v cc 16 v cc 15 qif out 14 aft sw/npsw 13 limiter in vco coil vco coil vreg. out vreg. out video out aft out rf agc apc video det eq amp if agc qif amp qif agc qif det v cc reg vco af amp fm det inter split lim amp aft pin arrangement 1 24 12 7 6 5 4 3 2 rf agc delay audio out gnd gnd vif in vif in rf agc out aft out eq f/b (top view) M52342FP outline: prsp0024ga-a (24p2q-a) limiter in vco coil vco coil vreg. out vreg. out video out apc filter 18 19 20 21 22 23 13 11 8 nfb gnd aft sw/npsw v cc 14 17 9 qif det in v cc 16 10 if agc filter qif out 15
M52342FP rev.2.00 jun 14, 2006 page 3 of 18 absolute maximum ratings (ta = 25 c, surge protection capacitance 200 pf resistance 0, unless otherwise noted) item symbol ratings unit condition supply voltage1 v cc 13.2 v v cc and vreg. out is not connected to each other. supply voltage vreg. out vreg. out 6.0 v v cc and vreg. out is not connected to each other. power dissipation pd 1524 mw operating temperature topr ? 20 to + 75 c storage temperature tstg ? 40 to + 150 c surge voltage resistance surge 200 v ambient operating condition (ta = 25 c, unless otherwise noted) supply voltage supply voltage range recommended supply voltage in case of v cc and vreg. out short 4.75 to 5.25 v 5.0 v in case of vreg. out open 8.5 to 12.5 v electrical characteristics (v cc = 5 v, ta = 25 c, unless otherwise noted) test conditions limits external power supply item sym bol te st ci rc uit test point input point input sg min. typ. max. unit v7 v8 v12 switches set to position 1 unless otherwise indicated vif section circuit current1 v cc = 5v i cc1 1 a vif in sg1 33 46 59 ma 5 v cc = 5v sw17 = 1, sw14 = 2 circuit current2 v cc = 12v i cc2 1 a vif in sg1 33 46 59 ma 5 v cc = 12v sw14 = sw17 = 2 vreg voltage v cc2 1 tp17 4.60 4.95 5.30 v 5 v cc = 12v sw7 = 2 video output dc voltage v18 1 tp18a 3.2 3.5 3.8 v 0 sw8 = 2 video output voltage v o det 1 tp18a vif in sg1 1.8 2.1 2.4 v p-p video s/n video s/n 1 tp18b vif in sg2 51 56 ? db sw18 = 2 video band width bw 1 tp18a vif in sg3 7.0 9.0 ? mhz va ria bl e sw8 = 2 input sensitivity vin min 1 tp18a vif in sg4 ? 48 52 db
M52342FP rev.2.00 jun 14, 2006 page 4 of 18 (v cc = 5 v, ta = 25 c, unless otherwise noted) test conditions limits external power supply item sym bol te st ci rc uit test point input point input sg min. typ. max. unit v7 v8 v12 switches set to position 1 unless otherwise indicated maximum allowable input vin max 1 tp18a vif in sg5 101 105 ? db agc control range input gr 50 57 ? db if agc voltage v8 1 tp8 vif in sg6 2.9 3.2 3.5 v maximum if agc voltage v8h 1 tp8 4.0 4.4 ? v minimum if agc voltage v8l 1 tp8 vif in sg7 2.2 2.4 2.6 v 4.2 4.7 ? 8.0 8.9 ? (v cc = 9v) maximum rf agc voltage v3h 1 tp3 vif in sg6 11.0 11.9 ? v (v cc = 12v) ? 0.1 0.5 ? 0.2 0.7 (v cc = 9v) minimum rf agc voltage v3l 1 tp3 vif in sg7 ? 0.2 0.7 v (v cc = 12v) rf agc operation voltage v3 1 tp3 vif in sg8 89 92 95 db capture range u cl-u 1 tp18a vif in sg9 1.0 1.7 ? mhz capture range l cl-l 1 tp18a vif in sg9 1.8 2.4 ? mhz capture range t cl-t 1 3.1 4.1 ? mhz aft sensitivity 1 tp2 vif in sg10 20 30 60 mv/ khz 3.3 3.85 4.15 ? 7.7 8.1 ? (v cc = 9v) aft maximum voltage v2h 1 tp2 vif in sg10 10.7 11.1 ? v 3.3 (v cc = 12v) ? 0.7 1.2 ? 0.7 1.2 (v cc = 9v) aft minimum voltage v2l 1 tp2 vif in sg10 ? 0.7 1.2 v 3.3 (v cc = 12v) 2.2 2.5 2.8 4.1 4.5 4.9 (v cc = 9v) aft defeat1 aft def1 1 tp2 vif in sg10 5.5 6.0 6.5 v 1.6 5 (v cc = 12v) 2.2 2.5 2.8 4.1 4.5 4.9 (v cc = 9v) aft defeat2 aft def2 1 tp2 vif in sg10 5.5 6.0 6.5 v 4.6 (v cc = 12v) inter modulation im 1 tp18a vif in sg11 35 40 ? db va ria bl e sw8 = 2
M52342FP rev.2.00 jun 14, 2006 page 5 of 18 (v cc = 5 v, ta = 25 c, unless otherwise noted) test conditions limits external power supply item sym bol te st ci rc uit test point input point input sg min. typ. max. unit v7 v8 v12 switches set to position 1 unless otherwise indicated differential gain dg 1 tp18a vif in sg12 ? 2 5 % differential phase dp 1 tp18a vif in sg12 ? 2 5 deg sync. tip level v18 sync 1 tp18a vif in sg2 0.85 1.15 1.45 v vif input resister rinv 2 tp4 ? 1.2 ? k ? vif input capacitanc e cinv 2 tp4 ? 5 ? pf sif section qif output1 qif1 1 tp13 vif in qif in sg2 sg13 94 100 106 db qif output2 qif2 1 tp13 vif in qif in sg2 sg14 94 100 106 db sif detection output v os 1 tp13 vif in sg15 94 100 106 db 0 5 sw7 = 2 af output dc voltage v1 1 tp10 sif in sg20 1.6 2.2 2.8 v 5 af output (4.5mhz) voaf 1 1 tp10 sif in sg16 400 560 800 mvr ms 5 af output (5.5mhz) voaf 2 1 tp10 sif in sg21 320 450 630 mvr ms 0 af output distortion (4.5mhz) thd af1 1 tp10 sif in sg16 ? 0.2 0.9 % 5 af output distortion (5.5mhz) thd af2 1 tp10 sif in sg21 ? 0.2 0.9 % 0 limiting sensitivity (4.5mhz) lim1 1 tp10 sif in sg17 sg19 ? 42 55 db 5 limiting sensitivity (5.5mhz) lim2 1 tp10 sif in sg22 sg24 ? 42 55 db 0 am rejection (4.5mhz) amr1 1 tp10 sif in sg18 55 62 ? db 5 am rejection (5.5mhz) amr2 1 tp10 sif in sg23 55 64 ? db 0 af s/n (4.5mhz) af s/n1 1 tp10 sif in sg20 55 62 ? db 5 af s/n (5.5mhz) af s/n2 1 tp10 sif in sg25 55 64 ? db 0
M52342FP rev.2.00 jun 14, 2006 page 6 of 18 (v cc = 5 v, ta = 25 c, unless otherwise noted) test conditions limits external power supply item sym bol te st ci rc uit test point input point input sg min. typ. max. unit v7 v8 v12 switches set to position 1 unless otherwise indicated sif input resistance rins 2 tp7 ? 1.5 ? k ? sif input capacitanc e cins 2 tp7 ? 4 ? pf control section qif control c qif 1 tp7 ? 0.7 1.0 v va ria bl e sw7 = 2 pin 14 voltage control pin 14 voltage (v) af aft 0 to 0.6 normal 0 to 2.3 1.0 to 2.3 pal defeat 2.7 to 4.0 normal 2.7 to 5.0 4.4 to 5.0 ntsc defeat electrical characteristics test method video s/n input sg2 into vif in and measure the video out (pin 22) noise in r.m.s at tp22b through a 5 mhz (?3 db) l.p.f. s/n = 20 log (db) 0.7 ? vo det noise bw video band width 1. measure the 1mhz component level of eq output tp22a with a spectrum analyzer when sg3 (f2 = 57.75 mhz) is input into vif in. at that time, measure the voltage at tp10 with sw10, set to position 2, and then fix v10 at that voltage. 2. reduce f2 and measure the value of (f2 ? f0) when the (f2 ? f0) component level reaches ? 3 db from the 1 mhz component level as shown below. tp18 1 mhz bw (f2 ? f0) ? 3 db
M52342FP rev.2.00 jun 14, 2006 page 7 of 18 vin min input sensitivity input sg4 (vi = 90 db ) into vif in, and then gradually reduce vi and measure the input level when the 20 khz component of eq output tp22a reaches ? 3 db from v o det level. vin max maximum allowable input 1. input sg5 (vi = 90 db ) into vif in, and measure the level of the 20 khz component of eq output. 2. gradually increase the vi of sg and meas ure the input level when the output reaches ? 3 db. gr agc control range gr = vin max ? vin min (db) v3 rf agc operating voltage input sg8 into vif in, and gradually reduce vi and then measure the input level when rf agc output tp3 reaches 1/2 v cc , as shown below. tp3 voltage 1/2 v cc v 3h v 3l vi vi (db ) cl-u capture range 1. increase the frequency of sg9 until the vco is out of locked-oscillation. 2. decrease the frequency of sg9 and measur e the frequency fu when the vco locks. cl-u = fu ? 58.75 (mhz) cl-l capture range 1. decrease the frequency of sg9 until the vco is out of locked-oscillation. 2. increase the frequency of sg9 and measur e the frequency fl when the vco locks. cl-l = 58.75 ? fl (mhz) cl-t capture range cl-t = cl-u + cl-l (mhz)
M52342FP rev.2.00 jun 14, 2006 page 8 of 18 aft sensitivity, v 2h maximum aft voltage, v 2l minimum aft voltage 1. input sg10 into vif in, and set the frequency of sg10 so that the voltage of aft output tp2 is 3 v. this frequency is named f (3). 2. set the frequency of sg10 so that the aft output voltage is 2 v. this frequency is named f (2). 3. in the graph, maximum and minimum dc voltage are v 2h and v 2l , respectively. tp2 voltage 3 v 2 v f (3) f (2) f (mhz) v 2h v 2l = (mv/khz) 1000 (mv) f (2) ? f (3) (khz) im intermodulation 1. input sg11 into vif in, and measure eq output tp22a with an oscilloscope. 2. adjust agc filter voltage v10 so that the minimum dc level of the output waveform is 1.0 v. 3. at this time, measure, tp 22a with a spectrum analyzer. the intermodulation is defined as a difference between 920 khz and 3.58 mhz frequency components. lim limiting sensitivity 1. input sg17 (sg22) into sif input, and measure the 400 hz component level of af output tp12. 2. input sg19 (sg24) into sif input, and measure the 400 hz component level of af output tp12. 3. the input limiting sensitivity is defi ned as the input level when a differe nce between each 400 hz components of audio output (tp12) is 30 db, as shown below. (db ) 30 db a udio output (mvrms) audio output while sg17 (sg22) is input audio output while sg19 (sg24) is input sif input amr am rejection 1. input sg18 (sg23) into sif input, and measure the output level of af output tp12. this level is named vam. 2. amr is; a mr = 20 log (db) voaf (mvrms) vam (mvrms)
M52342FP rev.2.00 jun 14, 2006 page 9 of 18 af s/n 1. input sg19 (sg24) into sif input, and measure the output noise level of af output tp1. this level is named vn. 2. s/n is; s/n = 20 log (db) voaf (mvrms) vn (mvrms) c qif qif control lower the voltage of v9, and measure the voltage of v9 when dc voltage of tp15 begins to change. the note in the system setup M52342FP has 2 power supply pins of v cc (pin 16, 17) and vreg. out (pin 20, 21) . v cc is for aft output, rf agc output circuits and 5 v regulated power circuit and vreg. out is for the other circuit blocks. in case M52342FP is used together with other ics like vif operating at more than 5 v, the same supply voltage as that of connected ics is applied to v cc and vreg. out is opened. the other circuit blocks, connected to vreg. out are powered by internal 5 v regulated power supply. in case the connecting ics are operated at 5 v, 5 v is supplied to both v cc and vreg. out. logic table af aft 20 k ?h? defeat 10 k ?h? 20 k ?l? ntsc normal 20 k ?h? defeat 10 k ?l? 20 k ?l? pal normal
M52342FP rev.2.00 jun 14, 2006 page 10 of 18 input signal sg no. signals (50 ? termination) 1 f 0 = 58.75 mhz am 20 khz 77.8 % 90 db 2 f 0 = 58.75 mhz 90 db cw 3 f 1 = 58.75 mhz 90 db cw (mixed signal) f 2 = frequency variable 70 db cw (mixed signal) 4 f 0 = 58.75 mhz am 20 khz 77.8 % level variable 5 f 0 = 58.75 mhz am 20 khz 14.0 % level variable 6 f 0 = 58.75 mhz 80 db cw 7 f 0 = 58.75 mhz 110 db cw 8 f 0 = 58.75 mhz cw level variable 9 f 0 = variable am 20 khz 77.8 % 90db 10 f 0 = variable 90db cw 11 f 1 = 58.75 mhz 90 db cw (mixed signal) f 2 = 55.17 mhz 80 db cw (mixed signal) f 3 = 54.25 mhz 80 db cw (mixed signal) 12 f 0 = 58.75 mhz 87.5 % tv modulation ten-step waveform sync tip level 90 db 13 f 1 = 54.25 mhz 95 db cw 14 f 1 = 54.25 mhz 75 db cw 15 f 1 = 58.75 mhz 90 db cw (mixed signal) f 2 = 54.25 mhz 70 db cw (mixed signal) 16 f 0 = 4.5 mhz 90 db fm 400 hz 25 khz dev 17 f 0 = 4.5 mhz fm 400 hz 25 khz dev level variable 18 f 0 = 4.5 mhz 90 db am 400 hz 30 % 19 f 0 = 4.5 mhz 90db cw 20 f 0 = 4.5 mhz cw level variable 21 f 0 = 5.5 mhz 90db fm 400 hz 50 khz dev 22 f 0 = 5.5 mhz fm 400 hz 50 khz dev level variable 23 f 0 = 5.5 mhz 90 db am 400 hz 30 % 24 f 0 = 5.5 mhz 90db cw 25 f 0 = 5.5 mhz cw level variable typical characteristics thermal derating (maximum rating) ambient temperature ta (c) 1750 1500 1250 1524 914 1000 750 500 250 0 ?20 0 25 50 75 100 125 150 power dissipation pd (mw)
M52342FP rev.2.00 jun 14, 2006 page 11 of 18 typical application example (for 38.9 mhz split) vif amp rf agc apc video det eq amp if agc qif amp qif agc qif det v cc reg vco af amp fm det lim amp aft 1 2 3 4 5 6 7 8 9 10 11 12 1 k 39 k 10 p 100 h 0.01 0.01 1 p vco coil 5531 20 19 18 17 16 0.01 24 23 22 21 15 14 13 + 33 + 0.47 10 k 2200 p 62 0.01 5.1 k 2.4 k units r: ? c: f note: in case the other components are connected to the gnd area nearby the vco coil, a leakage interference to them should be considered. the bypass capacitors of 33 f and 0.01 f are grounded as close as possible to the gnd pins (pin 6, 7, 8) so as to minimize the interference. 20 k off sfe 5.5md on on off 10 k 22 p 47 h 18 h v cc 8.5 to 12 v gnd 82 p 220 k 300 1 k 0.56 h 220 h 150 33 51 15 k 36 k 180 47 + 10 + 0.47 0.01 0.01 0.01 390 0.33 1 k saw 0.01 0.01 150 k 150 k 910 3.9 k if in inter split
M52342FP rev.2.00 jun 14, 2006 page 12 of 18 pin description pin 1 (rf agc delay) an applied voltage to the pin 1 is for changing a rf agc delay point. 1 v cc pin 2 (aft out) 2 the maximum outflow current is 0.2 ma. the maximum inflow current is 0.2 ma. tuner v cc since an aft output is provided by a high impedance source, the detection sensitivity can be set by an external resistor. the muting operation will be on in following two cases; 1) the apc is out of locking, 2) the video output becomes small enough in a weak electric field. (in open-loop condition) v cc 0 (fo) (v2) v cc 2 pin 3 (rf agc out) a current mode output is available in the reverse agc operation. the fluctuation of a bottom voltage is made small by loading higher impedance for a deep saturation. (in open-loop condition) (v3) v cc strong electric field weak electric field 0 (if input) (supply voltage to a tuner) 3 the maximum inflow current is 1.5 ma. tuner v cc (supply to a tuner) note: connecting a nonpolarity capacitor of 1 f between pin1 and pin3 improves agc operating speed. in that case, the capacitors betw een pin1/pin3 and ground should be removed. pin 4, pin 5 (vif in) it should be designed considering careful impedance matching with the saw filter. 5 4 bias 1.2 k 1.2 k saw terminal voltage : 1.45 v
M52342FP rev.2.00 jun 14, 2006 page 13 of 18 pin 6, pin 7, pin 8 (gnd) they are all groung pins. 6 7 8 pin 9 (qif det in) the input impedance is 1.5 k ? . in the intercarrier system application, the intercarrier output is available in pin 15 by connecting pin 9 to ground. 9 terminal voltage : 2.4 v inter/sprit inter bias 5 k 1.5 k 1.5 k saw pin 10 (if agc filter) 10 1 k v cc in spite of the 1-pin filter configuration, 2-pin filter characteristics are available by utilizing the dynamic agc circuit. weak electric field strong electric field (if input) (v10) 0 pin 11 (nfb) the fm detector can respond to several kinds of sif signals without an adjustment and external components by adopting the pll technique. it also is in compliance with the multi-sif by selecting an appropriate deemphasis and audio output amplifier using the pin 14 switch. the capacitor between pin 11 and 12, which fixes the deemphasis characteristics, can be determined considering the combination of an equivalent resistance of the ic and this capacitor itself. 11 terminal voltage : 2.1 v 5 k 5 k +
M52342FP rev.2.00 jun 14, 2006 page 14 of 18 pin 12 (audio out) terminal voltage: 2.2 v 12 in the 4.5 mhz application, the internal voltage gain is increased by 6-db in comparison with the other applications and then the signals are delivered through an emitter follower. pin 13 (limiter in) the input impedance is 8 k ? . 13 bias terminal voltage: 2.2 v 8 k 8 k pin 14 (aft sw/npsw) 22 k v cc (5 v) 2 k 14 10 k aft defeat : h aft on : l sif 4.5 mhz : h others : l it works as a switch by connecting the resistor to 5 v (high) or gnd (low), alternately. the terminal voltage is set by the external resistors because of an open base input. 10k h h l l 20k h l h l af amp 4.5 mhz 4.5 mhz other other aft defeat normal defeat normal pin 14 applied voltage 4.4 to 5.0 v 2.7 to 4.0 v 1.0 to 2.3 v 0 to 0.6 v pin 15 (qif out) in both the split and intercarrier system, the carrier signal to sif provided from pin 15 through an emitter follower. 15 terminal voltage: 2.45 v drive current : 0.5 ma. pin 16, pin 17 (v cc ) the recommended supply voltage is 5 v or 9 to 12 v. in the case of 5 v supply, these pins should be tied to pin 20 and pin 21. in the case of 9 to 12 v supply, a regulated output of 5 v are available in pin 20 and pin 21. 16 17 + v cc
M52342FP rev.2.00 jun 14, 2006 page 15 of 18 pin 18, pin 19 (vco coil) connecting a tuning coil and capacitor to these pins enables an oscillation. the tuning capacitor of about 30 pf is recommended. the oscillation frequency is tuned in f0. in the actual adjustment, the coil is tuned so that the aft voltage is reached to v cc /2 with f0 as an input. the printed pattern around these pins should be designed carefully to prevent an pull-in error of vco, caused by the laekage interference from the large signal level oscillator to adjacent pins. the interconnection also should be designed as short as possible. 18 19 466 850 466 850 pin 20, pin 21 (vreg. out) it is a regulated 5 v output which has current drive capability of approximately 15 ma. + 12.1 k 3.8 k 20 21 pin 22 (video out) internal driving current: 3 ma 22 an output amplitude is positive 2 v p-p in the case of 87.5% video modulation. 1.1 v o-p
M52342FP rev.2.00 jun 14, 2006 page 16 of 18 pin 23 (apc filter) 23 bias + in the locked state, the cut-off frequency of the filter is adjusted effectively by an external resistor so that it will be in the range of around 30 to 200 khz. in case the cut-off frequency is lower, the pull-in speed becomes slow. on the other hand, a higher cut-off frequency widen the pull-in range and band width, which results in a degradation in the s/n ratio. so, in the actual tv system design, the appropriate constant should be chosen for getting desirable performance considering above conditions. (v23) 3.4 v o-p fo (if input frequency) (fm mod. frequency) 100 khz (pin 23 output) a buzz noise also decreases by connecting a capacitor from pin 23 to v cc (pin 21) or gnd. this effect utilizes the signal interference on the printed circuit board. so, the determination that which connection is effective, to v cc or gnd, is done by a cut and try method. the capacitor of less than 680 pf, which depends on q of vco coil, is recommended to prevent an apc pull-in range from narrowing. taking it into consideration in the actual tv set design. in the application, an offset between aft center frequency and vco free-running frequency, can be improved by connecting a 220 k ? resistor to v cc supply (pin 21). 23 21 + 220 k c
M52342FP rev.2.00 jun 14, 2006 page 17 of 18 pin 24 (eq f/b) 24 + 3.9 k 16.8 k 3.1 k 500 both the external coil and capacitor determine the frequency response of eq output. the series connected resistor is for damping. 1.1 v o-p in the intercarrier system, the following phenomenon should be considered; a strong equalization (eq) enlarge the sound carrier output from pin 22, because the eq is applied before an audio trap. in that case, the next two solutions are recommended; decrease in s level of saw, avoiding to peak a sound carrier in eq. 3.17 k 22 24 video output 500 3.75 ma + ? 3.1 k video det. circuit diagram of eq amp.
M52342FP rev.2.00 jun 14, 2006 page 18 of 18 package dimensions f 1 12 13 24 *2 *1 *3 index mark y e h e e b p d a c detail f a 1 a 2 l include trim offset. dimension "*3" does not note) do not include mold flash. dimensions "*1" and "*2" 1. 2. a 1 0 0.1 0.2 previous code jeita package code renesas code prsp0024ga-a 24p2q-a mass[typ.] 0.2g p-ssop24-5.3x10.1-0.80 0.25 0.2 0.18 0.45 0.35 0.3 max nom min dimension in millimeters symbol reference 10.2 10.1 10.0 d 5.4 5.3 5.2 e 1.8 a 2 8.1 7.8 7.5 2.1 a 0.8 0.6 0.4 l 8 0 c 0.8 e 0.10 y h e b p 0.65 0.95
keep safety first in your circuit designs! 1. renesas technology corp. puts the maximum effort into making semiconductor products better and more reliable, but there is a lways the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placeme nt of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas t echnology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents i nformation on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvement s or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distrib utor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies o r errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas techn ology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, a nd algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under ci rcumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerosp ace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corp. is necessary to reprint or reproduce in whole or in part these materi als. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a lic ense from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corp. for further details on these materials or the products contained therein. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to " http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology (shanghai) co., ltd. unit 204, 205, aziacenter, no.1233 lujiazui ring rd, pudong district, shanghai, china 200120 tel: <86> (21) 5877-1818, fax: <86> (21) 6887-7898 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, 1 canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2730-6071 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas technology korea co., ltd. kukje center bldg. 18th fl., 191, 2-ka, hangang-ro, yongsan-ku, seoul 140-702, korea tel: <82> (2) 796-3115, fax: <82> (2) 796-2145 renesas technology malaysia sdn. bhd unit 906, block b, menara amcorp, amcorp trade centre, no.18, jalan persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: <603> 7955-9390, fax: <603> 7955-9510 renesas sales offices ? 200 6. re nesas technology corp ., all rights reser v ed. printed in ja pan. colophon .6.0

▲Up To Search▲

Price & Availability of M52342FP

	To Download M52342FP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .